Semiconductor package having flash-free contacts and techniques for manufacturing the same

ABSTRACT

Techniques for forming packaged semiconductor devices having top surfaces with flash-free electrical contact surfaces are described. According to one aspect, a molding cavity is provided which has a molding surface that is sufficiently smooth such that when placed in contact with an electrically conductive contact, gaps between the conductive contact and the mold cavity surface do not form.

CROSS-REFERENCE TO RELATED APPLICATIONS

This is a Divisional application of co-pending prior U.S. applicationSer. No. 10/274,056 (Atty. Dkt. No. NSC1P245/P05326), entitled“TECHINIQUES FOR MANUFACTURING FLASH-FREE CONTACTS ON A SEMICONDUCTORPACKAGE”, filed on Oct. 17, 2002, which is incorporated herein byreference and from which priority under 35 U.S.C. § 120 is claimed.

This application is related to U.S. Pat. No. 6,364,542, filed May, 9,2000, entitled “Device and Method for Providing a True Semiconductor toExternal Fiber Optic Cable Connection,” to U.S. patent application Ser.No. 09/922,598 (Attorney Docket No. NSC1P205), filed Jul. 11, 2001,entitled “Techniques for Joining an Optoelectronic Module to aSemiconductor Package”, to U.S. patent application Ser. No. 09/822,601(Attorney Docket No. NSC1P212), filed Aug. 14, 2001, entitled “OpticalSub-Assembly for Opto-Electronic Modules”, to U.S. patent applicationSer. No. 09/963,039 (Attorney Docket No. NSC1P215), filed Sep. 18, 2001,entitled “Techniques for Attaching Rotated Photonic Devices to anOptical Sub-Assembly in an Optoelectronic Package”, and to U.S. patentapplication Ser. No. 10/165,711 (Attorney Docket No. NSC1P212X1), filedJun. 6, 2002, entitled “Ceramic Optical Sub-Assembly for Opto-ElectronicModules,” the content of each of which are hereby incorporated byreference.

FIELD OF THE INVENTION

The present invention relates generally to semiconductor packagingprocesses, and more specifically to manufacturing semiconductor packageshaving flash-free electrical contact surfaces.

BACKGROUND OF THE INVENTION

In conventional semiconductor packaging processes, a resin material isused to encapsulate the semiconductor die. Since these packages need tobe connected to printed circuit boards or other devices, it is necessaryto avoid depositing the resin on the electrical contact leads. Thetypical mold cavity does not form a perfect seal with the surfaces andedges of the device enclosed by the cavity. Wherever gaps exist betweenthe mold cavity and the device, there is a potential for resin materialto be deposited in unwanted areas. This unwanted layer of mold compoundresin, or resin and fillers is called flash. The thickness of the flashcan vary from a thickness of a few microns up to a thickness of tens ofmicrons and depends on the composition of the mold compound (e.g. epoxyresin and filler distribution and size), the mold press clampingtonnage, the mold pressure used, and the design of the tool cavity. Whenflash forms on electrical contact leads, for instance, post-platingoperations cannot proceed since metal cannot be deposited on theinsulating layer. Typically, flash can be removed by a number ofoperations such as, but not limited to, sandblasting, wet chemicalexposure, and flame-off.

Flash is especially troubling when implementing the solder uplinkconcept disclosed in U.S. Pat. No. 6,364,542, “Device and method forproviding a true semiconductor die to external fiber optic cableconnection”, which is hereby incorporated in its entirety by reference.FIG. 1 illustrates a cross-sectional view of a stacked molded package asconstructed according to current manufacturing techniques. The solderuplink concept, illustrated in FIG. 1, involves the fabrication of astacked molded package 100 by connecting a mother package 105 to adaughter package 155 through solder bump pads 115. The problem is thatit has been found that the typical transfer molding operation withstandard mold tooling creates a thin flash layer covering some or all ofthe top surfaces of the solder bump pads 115 that are intended to beexposed through the molding material 135 on the mother package 105. FIG.2A illustrates an isometric view of the injection molding process. InFIG. 2A, the molding compound 135 is shown flowing across the motherintegrated circuit die 110. Note that the inside bottom surface 210 ofthe mold cavity 215 makes contact with the top surface of the solderballs 115. Note further the formation of flash 200 on the top surface ofthe solder balls 115. Specifically, flash 200 is represented wheremolding material 135 flows onto the top surfaces of solder balls 115.This occurs because a standard mold chamber has surfaces that are notcompletely smooth. Typically, a mold chamber surface will have aroughness of approximately 1.2 R_(A) (micron average roughness) or more.The roughness of the mold chamber surface allows gaps 205 to formbetween the inside surface 210 of the mold chamber and the top surfaceof the solder balls 115. Molding resin and/or fillers seep betweeninside bottom surface 210 of mold cavity 215 and the tops of the solderbump pads 115. FIG. 2B illustrates a magnified view of how moldingmaterial 135 flows into gaps 205 left between inside bottom surface 210and the surface of solder bump pads 115, causing flash 200. In thiscase, flash is catastrophic since the resin layer prevents goodmechanical and electrical contact between solder balls 115 on motherpackage 100 and solder balls 150 on daughter package 155.

Unfortunately, conventional means of removing flash are not desirablesince they are slow and require additional equipment. It is desirable todevelop techniques for creating flash free solder bump contacts on thetop surface of semiconductor packages without the use of additionalequipment or processing steps. Eliminating flash in the production ofthe mother package 100 will simplify the manufacturing steps, reducecosts, and enhance the reliability of the resulting module.

BRIEF SUMMARY OF THE INVENTION

The present invention is directed to an apparatus that satisfies theneed to create flash free electrical contacts on the top surface ofsemiconductor packages without the need for additional equipment orprocessing steps after the injection molding step. The apparatusincludes a molding chamber with a top molding cavity that has anexceptionally smooth inside surface. The smooth surface allows forbetter contact between the top molding cavity and the tops of theelectrical contacts on the top surface of a given semiconductor package,which in turn prevents molding material from flowing between the surfaceof the molding cavity and the tops of the electrical contacts. Theresult is that the electrical contacts are substantially flash freeafter the injection molding step.

As an apparatus, one embodiment of the present invention includes atleast a molding chamber including a bottom molding cavity to support asemiconductor die and a top molding cavity with an inside surface havinga surface roughness of approximately less than 1.2 R_(A).

As a method, one embodiment of the present invention includes at leastproviding the apparatus described above, placing a semiconductor devicewith an array of electrical connectors on its top surface in theapparatus, lowering the top molding cavity onto the semiconductor devicesuch that the molding cavity comes into direct contact with the array ofelectrical connectors, and injecting molding compound into the moldingcavity such that there is no flash formation on the top surfaces of theelectrical connectors.

These and other features and advantages of the present invention will bepresented in more detail in the following specification of the inventionand the accompanying figures, which illustrate by way of example theprinciples of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention, together with further advantages thereof, may best beunderstood by reference to the following description taken inconjunction with the accompanying drawings in which:

FIG. 1 illustrates a cross-sectional view of a stacked molded package asconstructed according to current manufacturing techniques.

FIG. 2A illustrates an isometric view of the injection molding process.

FIG. 2B illustrates a magnified view of how molding material flows intogaps formed between the molding cavity surface and the solder bumps.

FIG. 3A illustrates a side plan, cross-sectional view of a semiconductordie that is positioned within a molding chamber.

FIG. 3B illustrates a side-plan, cross-sectional view of semiconductordie that is enclosed within molding chamber.

FIG. 3C illustrates a magnified view of one of the electricallyconductive contacts of FIG. 3B.

FIG. 4 illustrates a perspective view of a mother semiconductor packageformed after the molding process described in FIGS. 3A and 3B.

DETAILED DESCRIPTION OF THE INVENTION

While the present invention will be described with reference to a fewspecific embodiments, the description is illustrative of the inventionand not to be construed as limiting the invention. Various modificationsto the present invention can be made to the preferred embodiments bythose skilled in the art without departing from the true spirit andscope of the invention as defined by the appended claims. It will benoted here that for a better understanding, like components aredesignated by like reference numerals throughout the various figures.

The present invention pertains to techniques for forming packagedsemiconductor devices having top surfaces with flash-free electricalcontact surfaces. The techniques involve using a molding cavity having asurface that is sufficiently smooth such that when placed in contactwith an electrically conductive contact, gaps between the conductivecontact and the mold cavity surface do not form. Molding materialtypically seeps into these gaps during molding processes and then curesinto flash formations. The present invention prevents flash from formingon contact surfaces by substantially eliminating the gaps between amolding cavity surface and the contact surface.

FIGS. 3A, 3B and 4 illustrate the process for forming packagedsemiconductor devices according to one embodiment of the presentinvention. First, FIG. 3A illustrates a side plan, cross-sectional viewof a semiconductor die 300 that is positioned within a molding chamber302. Semiconductor die 300 has a top surface 304 that contains contactpads upon which are formed electrically conductive contacts 306. In FIG.3A, semiconductor die 300 is mounted onto a die attach pad 308, however,die attach pad 308 is not required in alternative implementations of thepresent invention. Molding chamber 302 is formed by a top molding cavity310 and a bottom molding cavity 312.

After semiconductor die 300 is placed into molding chamber 302, topmolding cavity 310 is lowered onto bottom molding cavity 312. FIG. 3Billustrates a side-plan, cross-sectional view of semiconductor die 300that is enclosed within molding chamber 302. As top molding cavity 310is lowered onto bottom molding cavity 312, top molding cavity surface314 comes into contact with electrically conductive contacts 306 andcauses contacts 306 to deform. The substantially flat top molding cavitysurface 314 deforms the top portions of electrically conductive contacts306 so that they also have substantially flat surfaces. Electricallyconductive contacts 306 deform because they are typically made of amalleable material. In the embodiment shown, electrically conductivecontacts 306 are solder bumps.

In alternate embodiments, electrically conductive contacts 306 arealready flat prior to contact with top molding cavity surface 314 of topmolding cavity 312. Furthermore, such electrically conductive contactsneed not be malleable.

Top molding cavity surface 314 of top molding cavity 310 has a surfaceroughness of approximately less than 1.2 R_(A). This extremely smoothsurface forms an intimate contact with the tops of the electricallyconductive contacts 306, substantially minimizing the formation of gapsbetween the top molding cavity surface 314 of the top molding cavity 310and the tops of the electrically conductive contacts 306. In someembodiments of the invention, R_(A) is approximately equal to or lessthan 0.5. Further, in some embodiments of the invention, R_(A) isapproximately equal to or less than 0.1. Generally, as R_(A) decreases,fewer gaps are formed between top molding cavity surface 314 andelectrically conductive contacts 306 since top molding cavity surface314 will contain fewer surface imperfections such as recesses. Someembodiments of the present invention will employ a top molding cavity310 having top molding cavity surface 314 that has been made smooth bythe use of standard machine tools. Other embodiments will achieve thesame effect by applying a surface coating over top molding cavitysurface 314 that substantially smoothens the surface imperfections. Inyet other embodiments, top molding cavity surface 314 is manufactured tohave an average surface roughness of less than 1.2 R_(A) andadditionally provided with a surface coating for increased smoothness.Various materials, including metallic materials such as nickel, can beused as a surface coating material. Those skilled in the art willrecognize that other means of smoothing top molding cavity surface 314of top molding cavity 310 are also possible.

After semiconductor die 300 and electrically conductive contacts 306 areenclosed in molding chamber 302, a molding compound 316 is injected intomolding chamber 302. Because of the intimate contact between inside topsurface 314 and electrically conductive contacts 306, substantially nomolding compound seeps in between top molding cavity surface 314 andcontacts 306. This is because the intimate contact forces moldingcompound 316 to preferentially flow around the sides of contacts 306rather than over the top of contacts 306. Thus, there is substantiallyno flash formation on the top surface of the electrically conductivecontacts 306. See magnified view, FIG. 3C, showing a single electricallyconductive contact 306 with substantially no molding compound depositedbetween top molding cavity surface 314 and electrically conductivecontacts 306.

FIG. 4 illustrates a perspective view of a mother semiconductor package400 formed after the molding process described in FIGS. 3A-3C. The curedmolding compound 316 of semiconductor package 400 contains integratedcircuit die 300, die attach pad 308 and electrically conductive contacts306. Due to the constraints of top cavity molding surface 314,electrically conductive contacts 306 are exposed through the top surfaceof molding material 316. The top surfaces of contacts 306 are also flatand coplanar with the top surface of the cured molding compound 316.Advantageously, the top surfaces of electrically conductive contacts 306are substantially flash-free since the molding compound 316 did not flowbetween top cavity surface 314 of molding chamber 302 and the topsurfaces of contacts 306 during the molding process (see FIG. 3C).

The advantage of electrically conductive contacts 306 havingsubstantially flash-free top surfaces of is that the process ofattaching a daughter package 155 (as shown in FIG. 1) is simplified.This is because it is not necessary to perform post-molding processoperations such as sanding, buffering, or cleaning to remove flash fromthe top surfaces of electrically conductive contacts 306 beforeattaching the daughter package 155. Therefore, processes for attaching adaughter package can begin immediately after the molding process shownin FIG. 3B.

In one embodiment of the present invention, a Towa Model M60 Mold Press(referred to as “Towa press”) is used to carry out the injection moldingprocess. When using the Towa press, it has been found that the settingsin Table 1, Operational Settings for Towa Model M60 Mold Press in theContext of the Current Invention, provide acceptable results. TABLE 1Operational Settings for Towa Model M60 Mold Press in the Context of theCurrent Invention. Mold Setting Injection Setting Clamp Pressure CureTime: 80 sec. Transfer Pressure: Chase Pressure: 0.18 ton 2 tons MoldTemperature: Transfer Speed 1.8 170° C. to 2.0 m/s Clamp Pressure: 18-20tons

Note that the above settings may vary by as much as ±20% and continue toprovide acceptable results. It will be understood by those familiar withthe art that the injection molding process described in this applicationcan be carried out by using other mold presses or devices that usedifferent molding compound temperatures, pressures, and flow rates andthat the above operational settings are specific to the Towa Model M60Machine Press.

The cure time of 80 seconds is mold compound and temperature-dependent.Initiators and catalysts can be added in a number of combinations so toeither speed up, or slow down, the reaction time to reach a B-stagestate, which is sufficiently rigid to allow for mold removal withoutdamaging the parts for post mold cure. Typically, reaction speed needsto be balanced with the injection speed. A slow injection speed combinedwith fast reaction will lead to a rapid increase in the compoundviscosity, which may lead to a host of flow-induced problems such aswire sweep, voiding, and incomplete fill.

Mold temperature represents the temperature of the mold compound uponinjection into the molding chamber. This is the general mold setting,although some applications may call for settings as low as 150° C. andas high as 200° C. With the latter setting, the mold compound can reacha sufficiently advanced cured state such that post curing is no longerneeded.

Clamp pressure refers to the machine setting to keep the two mold halvesclamped shut. This value will be machine and mold-dependent. Aproduction mold will be larger and heavier and will therefore requiremore clamping tonnage.

Transfer pressure refers to the hydraulic force applied to the transferplunger, which presses the molding material into the molding chamber.The plunger typically presses on the molding material, which is heldwithin a chute. The Towa Model M60 uses a cylindrical mold compoundpellet that is 14 mm in diameter and which weighs 3.8 gm. Thistranslates into a machine-independent transfer pressure of 1,690 psi (or1.16 kg/mm²).

The transfer speed is the speed at which the molding material istransferred into the molding chamber from the chute. Transfer speedcontrols the shear rate imparted to the mold compound as it flows intothe mold cavities. Shear rate is the ratio of flow front velocity overthe gap that the front has to flow through. Its unit is inverse sec(s⁻¹). For the same transfer speed, the shear rate will vary as the gapis increased or decreased. In a mold cavity, the key gaps are thecross-section of the runner (from the pot containing the pellet), thegate (opening into the mold cavity), and the cavity upper and lower gaps(delineated by the leadframe or substrate). For a leadless leadframepanel (LLP) mold setting, the shear rates are estimated to be about 380s⁻¹, 8,100 s⁻¹, 430 s⁻¹ for the runner, gate, and cavity, respectively.Such numbers are based on the flow front velocity estimated at each oneof those locations. It is important to maintain those(machine-independent) settings to ensure that the proper filling of themold cavity can be achieved. Again, variations within 20% of thesemachine-independent values are acceptable.

Some mold presses have a two-stage clamping process. Large (global)clamping to provide rough clamping of large platens and small (local)clamping on the chase area. The small (local) pressure is also referredto as chase pressure. Chase pressure ensures that the large pressuredoes not all come down on the leadframe or substrate and crush thematerial. The small local clamping allows more flexibility infine-tuning the local pressure on certain areas of the mold andsubstrate or leadframe. Older presses have only one clamp pressuresetting.

Note that the transfer pressure and speeds in Table 1 describe thesettings for the Towa Model M60 Mold Press. Also provided above, are themachine-independent pressure and speed values. The machine-independentvalues describe the transfer pressure and speed within the moldingchamber regardless of the specific mold press dimensions andcharacteristics. The machine-independent values of the molding processare set so that injected molding material does not force its way betweenthe top cavity surface of a molding cavity and the conductive contactsuch that flash would form. The machine-independent pressure and speedof the molding material within a molding chamber should be approximatelythe same regardless of the specific molding press used.

In some embodiments, mother package 400 will be manufactured accordingto specific form factors. Form factors represent standard configurationsand dimensions for the die, die attach pad, wire leads, moldingmaterial, etc. of semiconductor packages. Some exemplary form factorsoffered in the portfolio of the National Semiconductor Corporation (NSC)include SOP (Small Outline Package), DIP (Dual In-Line Package), PGA(Pin Grid Array), LCC (Leaded Chip Carrier), QFP (Quad Flatpack), BGA(Ball Grid Array), and CSP (Chip Sized Package). It should be noted thatform factors not provided by NSC may also be suitable for thisinvention.

Furthermore, in some embodiments, a daughter package that is attached tomother package 400 can be an integrated circuit package, an opticalsubmodule such as an optoelectronic transceiver, transmitter orreceiver, or any other device suitable for connection to package 400 viaelectrically conductive contacts.

While this invention has been described in terms of several preferredembodiments, there are alterations, permutations, and equivalents, whichfall within the scope of this invention. It should also be noted thatthere are many alternative ways of implementing the methods andapparatuses of the present invention. It is therefore intended that thefollowing appended claims be interpreted as including all suchalterations, permutations, and equivalents as fall within the truespirit and scope of the present invention.

1. A semiconductor molding chamber comprising: a top molding cavityhaving a molding surface that has a surface roughness of less than 1.2R_(a); and a bottom molding cavity configured to support a semiconductordie, whereby the top and bottom molding cavity enclose the semiconductorwithin the molding chamber.
 2. A semiconductor molding chamber asrecited in claim 1 wherein the molding surface has a surface roughnessof approximately equal to or less than 0.5 R_(a).
 3. A semiconductormolding chamber as recited in claim 1 wherein the molding surface has asurface roughness of approximately equal to or less than 0.1 R_(a).
 4. Asemiconductor molding chamber as recited in claim 1 wherein the moldingsurface of the top molding cavity contains surface imperfections, themolding chamber further comprising: a surface coating formed over themolding surface of the top molding cavity that substantially smoothensthe surface imperfections.
 5. A semiconductor molding system comprising:a semiconductor die having a top surface and a bottom surface, at leastone deformable electrically conductive contact on the top surface; a topmolding cavity having a molding surface that has a surface roughness ofapproximately equal to or less than 1.2 R_(a), wherein the moldingsurface is in contact with the deformable electrically conductivecontact; and a bottom molding cavity that supports the semiconductordie.
 6. A semiconductor molding system as recited in claim 5 wherein themolding surface has a surface roughness of approximately equal to orless than 0.5 R_(a).
 7. A semiconductor molding system as recited inclaim 5 wherein the molding surface has a surface roughness ofapproximately equal to or less than 0.1 R_(a).
 8. A semiconductormolding system as recited in claim 5 wherein the molding surface of thetop molding cavity contains surface imperfections, the molding systemfurther comprising: a surface coating formed over the molding surface ofthe top molding cavity that substantially smoothens the surfaceimperfections.
 9. A semiconductor molding system as recited in claim 5wherein the deformable electrically conductive contact is a solder ball.10. A method of packaging a semiconductor die comprising: providing atop molding cavity that has a top molding surface with a surfaceroughness of less than 1.2 R_(a); providing a bottom molding cavity thathas a bottom molding surface, wherein the top and the bottom moldingcavity form a molding chamber; placing the semiconductor die having oneor more deformable electrically conductive contacts on a top surface ofthe die into the molding chamber; lowering the top molding cavity ontothe deformable electrically conductive contacts such that the topmolding surface deforms the contacts and creates an empty space betweenthe top surface of the semiconductor die and the top molding surface;and injecting a molding compound into the molding chamber such that themolding compound surrounds the deformable electrically conductivecontacts and fills the empty space between the top surface of thesemiconductor die and the top molding surface in a way that no flashforms on a top surface of each of the deformable electrically conductivecontacts.
 11. A method as recited in claim 10 wherein the moldingcompound is injected into the molding chamber such that the moldingcompound flows through the molding chamber at 1.16 kg/mm².
 12. A methodas recited in claim 10 wherein the deformable electrically conductivecontacts are solder balls.
 13. A method as recited in claim 10 whereinthe packaged semiconductor die is formed after the injecting operation,the method further comprising: attaching a secondary device to a topsurface of the packaged semiconductor die such that electrical contactsof the secondary device make contact with the top surface of each of thedeformable electrically conductive contacts, wherein the attachingoperation is the next operation after the injecting operation.